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ISCAS
2005
IEEE
165views Hardware» more  ISCAS 2005»
14 years 4 months ago
An area-efficient and protected network interface for processing-in-memory systems
Abstract- This paper describes the implementation of an areaefficient and protected user memory-mapped network interface, the pbuf (Parcel Buffer), for the Data IntensiVe Architect...
Sumit D. Mediratta, Craig S. Steele, Jeff Sondeen,...
ISCC
2005
IEEE
119views Communications» more  ISCC 2005»
14 years 4 months ago
A Systematic Approach to Building High Performance Software-Based CRC Generators
—A framework for designing a family of novel fast CRC generation algorithms is presented. Our algorithms can ideally read arbitrarily large amounts of data at a time, while optim...
Michael E. Kounavis, Frank L. Berry
ISPAN
2005
IEEE
14 years 4 months ago
An FPGA-Based Floating-Point Jacobi Iterative Solver
Within the parallel computing domain, field programmable gate arrays (FPGA) are no longer restricted to their traditional role as substitutes for application-specific integrated...
Gerald R. Morris, Viktor K. Prasanna
MTV
2005
IEEE
138views Hardware» more  MTV 2005»
14 years 4 months ago
Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets
Microprocessor technology is increasingly used for many applications; the large market volumes call for cost containment in the production phase. Process yield for processor produ...
Paolo Bernardi, Ernesto Sánchez, Massimilia...
AOSD
2005
ACM
14 years 4 months ago
Modularizing design patterns with aspects: a quantitative study
Design patterns offer flexible solutions to common problems in software development. Recent studies have shown that several design patterns involve crosscutting concerns. Unfortun...
Alessandro F. Garcia, Cláudio Sant'Anna, Ed...