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ISCA
2012
IEEE
191views Hardware» more  ISCA 2012»
12 years 23 days ago
VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors
Power consumption is a primary concern for microprocessor designers. Lowering the supply voltage of processors is one of the most effective techniques for improving their energy e...
Timothy N. Miller, Renji Thomas, Xiang Pan, Radu T...
ISCA
2012
IEEE
218views Hardware» more  ISCA 2012»
12 years 23 days ago
Towards energy-proportional datacenter memory with mobile DRAM
To increase datacenter energy efficiency, we need memory systems that keep pace with processor efficiency gains. Currently, servers use DDR3 memory, which is designed for high b...
Krishna T. Malladi, Frank A. Nothaft, Karthika Per...
ISCA
2012
IEEE
224views Hardware» more  ISCA 2012»
12 years 23 days ago
A first-order mechanistic model for architectural vulnerability factor
Soft error reliability has become a first-order design criterion for modern microprocessors. Architectural Vulnerability Factor (AVF) modeling is often used to capture the probab...
Arun A. Nair, Stijn Eyerman, Lieven Eeckhout, Lizy...
ISCA
2012
IEEE
262views Hardware» more  ISCA 2012»
12 years 23 days ago
Boosting mobile GPU performance with a decoupled access/execute fragment processor
Smartphones represent one of the fastest growing markets, providing significant hardware/software improvements every few months. However, supporting these capabilities reduces the...
Jose-Maria Arnau, Joan-Manuel Parcerisa, Polychron...
ISCA
2012
IEEE
244views Hardware» more  ISCA 2012»
12 years 23 days ago
Scheduling heterogeneous multi-cores through performance impact estimation (PIE)
Single-ISA heterogeneous multi-core processors are typically composed of small (e.g., in-order) power-efficient cores and big (e.g., out-of-order) high-performance cores. The eff...
Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout...