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ISCA
2002
IEEE
14 years 2 months ago
2002
IEEE
This paper introduces the idea of using a User-Level Memory Thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main ...
ISCA
2002
IEEE
14 years 2 months ago
2002
IEEE
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
ISCA
2002
IEEE
14 years 2 months ago
2002
IEEE
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
ISCA
2002
IEEE
14 years 2 months ago
2002
IEEE
One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper will explore the relationship between ...
ISCAS
2002
IEEE
14 years 2 months ago
2002
IEEE
We present a CMOS circuit that utilizes the back-gate effect to extend the linear range of a subthreshold MOS transconductor. Previous designs of wide-linear-range transconductors...