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ISCAS
2003
IEEE
14 years 3 months ago
2003
IEEE
A massively scalable architecture for decoding low-density parity-check codes is presented in this paper. This novel architecture uses hardware scaling and memory partitioning to ...
ISCAS
2003
IEEE
14 years 3 months ago
2003
IEEE
2. COUPLED OSCILLATOR USING TRANSCONDUCTORS A CMOS neural oscillator using negative resistance has An ideal coupled oscillator using two operational been designed and fabricated i...
ISCAS
2003
IEEE
14 years 3 months ago
2003
IEEE
This paper studies simple hyperchaotic circuits consisting of one linear 3-port voltage-controlled current source (ab. VCCS), two linear capacitors and one dependent switched capa...
ISCAS
2003
IEEE
2003
IEEE
Bifurcation analysis of a power-factor-correction boost converter: uncovering fast-scale instability
14 years 3 months ago
Bifurcation analysis is performed to a power-factor-correction (PFC) boost converter to examine the fast-scale instability problem. Computer simulations and analysis reveal the po...
ISCAS
2003
IEEE
14 years 3 months ago
2003
IEEE
We consider adaptive fault diagnosis for array multiprocessor systems. We show that three testing rounds are necessary and sufficient for adaptive parallel diagnosis of an Nproce...