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ISCA
2003
IEEE
108views Hardware» more  ISCA 2003»
14 years 3 months ago
Effective ahead Pipelining of Instruction Block Address Generation
On a N-way issue superscalar processor, the front end instruction fetch engine must deliver instructions to the execution core at a sustained rate higher than N instructions per c...
André Seznec, Antony Fraboulet
ISCAS
2003
IEEE
167views Hardware» more  ISCAS 2003»
14 years 3 months ago
The multi-level paradigm for distributed fault detection in networks with unreliable processors
In this paper, we study the effectiveness of the multilevel paradigm in considerably reducing the diagnosis latency of distributed algorithms for fault detection in networks with ...
Krishnaiyan Thulasiraman, Ming-Shan Su, V. Goel
ISCAS
2003
IEEE
201views Hardware» more  ISCAS 2003»
14 years 3 months ago
A regularized simultaneous autoregressive model for texture classification
In this paper, we present a new method for texture classification which we call the regularized simultaneous autoregressive method (RSAR). The regularization technique is introduc...
Yao-wei Wang, Yan-fei Wang, Wen Gao, Yong Xue
ISCA
2003
IEEE
169views Hardware» more  ISCA 2003»
14 years 3 months ago
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, ...
ISCA
2003
IEEE
136views Hardware» more  ISCA 2003»
14 years 3 months ago
Transient-Fault Recovery for Chip Multiprocessors
To address the increasing susceptibility of commodity chip multiprocessors (CMPs) to transient faults, we propose Chiplevel Redundantly Threaded multiprocessor with Recovery (CRTR...
Mohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz,...