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ISCA
2008
IEEE
113views Hardware» more  ISCA 2008»
14 years 2 months ago
A Two-Level Load/Store Queue Based on Execution Locality
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
Miquel Pericàs, Adrián Cristal, Fran...
ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
14 years 2 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
ISCA
2008
IEEE
148views Hardware» more  ISCA 2008»
14 years 2 months ago
Atomic Vector Operations on Chip Multiprocessors
The current trend is for processors to deliver dramatic improvements in parallel performance while only modestly improving serial performance. Parallel performance is harvested th...
Sanjeev Kumar, Daehyun Kim, Mikhail Smelyanskiy, Y...
ISCAS
2008
IEEE
134views Hardware» more  ISCAS 2008»
14 years 2 months ago
Bidirectionally decodable Wyner-Ziv video coding
Abstract— Inter frame prediction technique significantly improves the compression efficiency in the hybrid video coding schemes. However, this technique causes the decoding dep...
Xiaopeng Fan, Oscar C. Au, Yan Chen, Jiantao Zhou,...
ISCAS
2008
IEEE
136views Hardware» more  ISCAS 2008»
14 years 2 months ago
Spatial-temporal consistent labeling for multi-camera multi-object surveillance systems
Abstract—For an intelligent multi-camera multi-object surveillance system, object correspondence across time and space is important to many smart visual applications. In this pap...
Jing-Ying Chang, Tzu-Heng Wang, Shao-Yi Chien, Lia...