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ISCAS
2005
IEEE
121views Hardware» more  ISCAS 2005»
14 years 2 months ago
On-board fault-tolerant SAR processor for spaceborne imaging radar systems
A real-timehigh-performanceand fault-tolerantFPGA-based hardware architecture for the processing of synthetic apertureradar (SAR) images has been developed for advanced spaceborner...
Wai-Chi Fang, C. Le, S. Taft
ISCAS
2005
IEEE
136views Hardware» more  ISCAS 2005»
14 years 2 months ago
Economical passive filter synthesis using genetic programming based on tree representation
—In this work we propose a novel tree representation for RLC circuits. Genetic programming based on the tree representation is described and applied to passive filter synthesis p...
Hao-Sheng Hou, Shoou-Jinn Chang, Yan-Kuin Su
ISCAS
2005
IEEE
138views Hardware» more  ISCAS 2005»
14 years 2 months ago
An high speed integrated equalizer for dispersion compensation in 10Gb/s fiber networks
—This paper presents the design of a high-speed analog transversal equalizer for dispersion compensation in 10Gb/s fiber networks. We present design details of a seven tap transv...
Vasanth Kakani, Foster F. Dai, Richard C. Jaeger
ISCAS
2005
IEEE
103views Hardware» more  ISCAS 2005»
14 years 2 months ago
Hardware realization of panoramic camera with speaker-oriented face extraction for teleconferencing
— In this paper, a panoramic camera with speaker oriented face extraction function is proposed. For the face extraction, the Genetic Algorithm(GA) is implemented in a Field Prgra...
Yukinori Nagase, Takahiko Yamamoto, Takao Kawamura...
ISCAS
2005
IEEE
141views Hardware» more  ISCAS 2005»
14 years 2 months ago
Convergence analysis of a background interstage gain calibration technique for pipelined ADCs
A mathematical framework for the convergence analysis of a pipelined ADC with background gain calibration is presented. The constraints on adaptation step size for mean convergenc...
Dong Wang, J. P. Keane, Paul J. Hurst, Bernard C. ...