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ISCAS
2005
IEEE
100views Hardware» more  ISCAS 2005»
14 years 1 months ago
A test strategy for time-to-digital converters using dynamic element matching and dithering
This work presents a cost-effective test structure that is applicable to built-in self-test of time-to-digital converters (TDCs). The proposed structure uses deterministic dynamic ...
Wenbo Liu, Hanqing Xing, Le Jin, Randall L. Geiger...
ISCA
2003
IEEE
89views Hardware» more  ISCA 2003»
14 years 1 months ago
MisSPECulation: Partial and Misleading Use of SPEC CPU2000 in Computer Architecture Conferences
A majority of the papers published in leading computer architecture conferences use SPEC CPU2000, or its predecessor SPEC CPU95, which has become the de facto standard for measuri...
Daniel Citron
ISCAS
2005
IEEE
119views Hardware» more  ISCAS 2005»
14 years 1 months ago
Analysis of power consumption in VLSI global interconnects
Abstract— The analysis of effects induced by interconnects become increasingly important as the scale of process technologies steadily shrinks. While most analyses focus on the t...
Youngsoo Shin, Hyung-Ock Kim
ISCAS
2005
IEEE
124views Hardware» more  ISCAS 2005»
14 years 1 months ago
Timing-driven global routing with efficient buffer insertion
-- Timing optimization is an important goal of global routing in deep submicron era. To guarantee the timing performance of the circuit, merely adopting topology optimization becom...
Jingyu Xu, Xianlong Hong, Tong Jing
ISCAS
2005
IEEE
140views Hardware» more  ISCAS 2005»
14 years 1 months ago
Drift-free multiple description video coding with redundancy rate-distortion optimization
— Multiple description coding (MDC) has been shown to be robust for video transmission over error-prone channels. By applying the extra prediction loops to the multiple descripti...
Yilong Liu, Soontorn Oraintara