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ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
— A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is presented in this paper. The unique feature of the proposed frequency synthesizer is a loo...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
— A phase-locked loop (PLL) with two different delay feedback paths is presented. It provides a new approach to minimize the dead zone, jitter accumulation, long settling time an...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
We describe an algorithm for self-organizing connections from a source array to a target array of neurons that is inspired by neural growth cone guidance. Each source neuron proje...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
—This paper presents a new electrostatic discharge (ESD) protection design for input/output (I/O) cells with embedded silicon-controlled rectifier (SCR) structure as power-rail E...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
— Switched dynamical systems are known to exhibit border collision, in which a particular operation is terminated and a new operation is assumed as one or more parameters are var...