A frequency synthesizer using two different delay feedbacks

— A phase-locked loop (PLL) with two different delay feedback paths is presented. It provides a new approach to minimize the dead zone, jitter accumulation, long settling time and nonidealities on PFD/CP. This PLL utilizes a tunable delay cell to reduce the ripple on the VCO control line and hence the jitter penalty. In addition, a fully differential delay cell for voltage-controlled oscillator (VCO) is introduced to perform a wide locking range and low-jitter performance. The proposed PLL was implemented in 0.35-µm 2P4M CMOS standard technology with the core area of 0.1 mm2 . It can be operated

• Type: Conference
• Year: 2005
• Where: ISCAS
• Authors: Chien-Hung Kuo, Yi-Shun Shih
• Keywords: Delay Cell, Delay Feedback Paths, ISCAS 2005, Tunable Delay Cell