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ISLPED
2004
ACM
88views Hardware» more  ISLPED 2004»
14 years 4 months ago
Architecting voltage islands in core-based system-on-a-chip designs
Voltage islands enable core-level power optimization for Systemon-Chip (SoC) designs by utilizing a unique supply voltage for each core. Architecting voltage islands involves isla...
Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu ...
ISLPED
2004
ACM
99views Hardware» more  ISLPED 2004»
14 years 4 months ago
Dynamic power management for streaming data
—This paper presents a method that uses data buffers to create long periods of idleness to exploit power management. This method considers the power consumed by the buffers and a...
Nathaniel Pettis, Le Cai, Yung-Hsiang Lu
ISLPED
2004
ACM
157views Hardware» more  ISLPED 2004»
14 years 4 months ago
4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors
We present a novel temperature/leakage sensor, developed for high-speed, low-power, monitoring of processors and complex VLSI chips. The innovative idea is the use of 4T SRAM cell...
Stefanos Kaxiras, Polychronis Xekalakis
ISLPED
2004
ACM
139views Hardware» more  ISLPED 2004»
14 years 4 months ago
Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...
Kim M. Hazelwood, David Brooks
ISLPED
2004
ACM
137views Hardware» more  ISLPED 2004»
14 years 4 months ago
Location cache: a low-power L2 cache system
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...
Rui Min, Wen-Ben Jone, Yiming Hu