Voltage islands enable core-level power optimization for Systemon-Chip (SoC) designs by utilizing a unique supply voltage for each core. Architecting voltage islands involves isla...
Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu ...
—This paper presents a method that uses data buffers to create long periods of idleness to exploit power management. This method considers the power consumed by the buffers and a...
We present a novel temperature/leakage sensor, developed for high-speed, low-power, monitoring of processors and complex VLSI chips. The innovative idea is the use of 4T SRAM cell...
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...