For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
Over the last five years the VLSI Placement community achieved great strides in the understanding of placement problems, developed new high-performance algorithms, and achieved i...
Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov...
— In order to achieve timing closure on increasingly complex IC designs, buffer insertion needs to be performed on thousands of nets within an integrated physical synthesis syste...
Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jia...
This paper presents a new timing driven force directed placement algorithm that meets physical net length constraints as well as constraints on specific pin sets. It is the first ...
Karthik Rajagopal, Tal Shaked, Yegna Parasuram, Tu...
Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate t...
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, ...