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ISPD
2006
ACM
103views Hardware» more  ISPD 2006»
14 years 2 months ago
High accurate pattern based precondition method for extremely large power/ground grid analysis
In this paper, we propose more accurate power/ground network circuit model, which consider both via and ground bounce effects to improve the performance estimation accuracy of on-...
Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hon...
DAC
2012
ACM
11 years 11 months ago
ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement
We develop a projected-subgradient primal-dual Lagrange optimization for global placement, that can be instantiated with a variety of interconnect models. It decomposes the origin...
Myung-Chul Kim, Igor L. Markov
ISPD
2006
ACM
175views Hardware» more  ISPD 2006»
14 years 2 months ago
mPL6: enhanced multilevel mixed-size placement
The multilevel placement package mPL6 combines improved implementations of the global placer mPL5 (ISPD05) and the XDP legalizer and detailed placer (ASPDAC06). It consistently pr...
Tony F. Chan, Jason Cong, Joseph R. Shinnerl, Kent...
ISPD
2006
ACM
90views Hardware» more  ISPD 2006»
14 years 2 months ago
Fast buffer insertion considering process variations
Advanced process technologies call for a proactive consideration of process variations in design to ensure high parametric timing yield. Despite of its popular use in almost any h...
Jinjun Xiong, Lei He
ISPD
2006
ACM
108views Hardware» more  ISPD 2006»
14 years 2 months ago
Statistical clock tree routing for robustness to process variations
Advances in VLSI technology make clock skew more susceptible to process variations. Notwithstanding efficient zero skew routing algorithms, clock skew still limits post-manufactu...
Uday Padmanabhan, Janet Meiling Wang, Jiang Hu