Unlike their hard realtime counterparts, soft realtime applications are only expected to guarantee their ”expected delay” over input data space. This paradigm shift calls for ...
- A low overhead circuit technique is proposed in this paper for simultaneously reducing subthreshold and gate oxide leakage currents in domino logic circuits. PMOS sleep transisto...
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper develops closed-form models to predict the dela...
Gate-length biasing is a runtime leakage reduction technique that leverages on the short-channel effect by marginally increasing the gate-length of MOS devices to significantly ...