A simulation-based feasibility study of an intra-chip wireless interconnect system is presented. The wireless interconnect system is modelled in a 250 nm standard complementary met...
— Post-silicon debug comprises a significant and highly variable fraction of the total development time for large chip designs. To accelerate post-silicon debug, BackSpace [1, 2...
Johnny J. W. Kuan, Steven J. E. Wilton, Tor M. Aam...
We present a method to abstract, formalize, and verify industrial flash memory implementations. Flash memories contain specialized transistors, e.g., floating gate and split gate d...
Sandip Ray, Jayanta Bhadra, Thomas Portlock, Ronal...
Abstract— As the semiconductor technology continues its marching toward the deep sub-micron domain, the strong relation between leakage current and temperature becomes critical i...