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ISVLSI
2007
IEEE
204views VLSI» more  ISVLSI 2007»
14 years 5 months ago
Designing Memory Subsystems Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz
ISVLSI
2007
IEEE
160views VLSI» more  ISVLSI 2007»
14 years 5 months ago
On the Limitations of Power Macromodeling Techniques
Although RTL power macromodeling is a mature research topic, it is not yet broadly accepted in the industrial environment. One of the main reasons impairing its widespread use as ...
Felipe Klein, Guido Araujo, Rodolfo Azevedo, Rober...
ISVLSI
2007
IEEE
127views VLSI» more  ISVLSI 2007»
14 years 5 months ago
Asymmetrically Banked Value-Aware Register Files
Designing high-performance low-power register files is of critical importance to the continuation of current performance advances in wide-issue and deeply-pipelined superscalar m...
Shuai Wang, Hongyan Yang, Jie Hu, Sotirios G. Ziav...
ISVLSI
2007
IEEE
121views VLSI» more  ISVLSI 2007»
14 years 5 months ago
Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor
Power line communications (PLC) using impulse ultra wideband (UWB) in a microprocessor had been proposed for ubiquitous access of internal nodes for test/debug purposes. In this p...
Rajesh Thirugnanam, Dong Sam Ha, T. M. Mak
ISVLSI
2007
IEEE
139views VLSI» more  ISVLSI 2007»
14 years 5 months ago
Automatic Retargeting of Binary Utilities for Embedded Code Generation
Contemporary SoC design involves the proper selection of cores from a reference platform. Such selection implies the design exploration of alternative CPUs, which requires the gen...
Alexandro Baldassin, Paulo Centoducatte, Sandro Ri...