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ISCA
2009
IEEE
146views Hardware» more  ISCA 2009»
14 years 4 months ago
Multi-execution: multicore caching for data-similar executions
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
Susmit Biswas, Diana Franklin, Alan Savage, Ryan D...
SBACPAD
2008
IEEE
100views Hardware» more  SBACPAD 2008»
14 years 4 months ago
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors
The performance impact of the Physical Register File (PRF) size on Simultaneous Multithreading processors has not been extensively studied in spite of being a critical shared reso...
Jesús Alastruey, Teresa Monreal, Francisco ...
DATE
2007
IEEE
100views Hardware» more  DATE 2007»
14 years 4 months ago
Working with process variation aware caches
Deep-submicron designs have to take care of process variation effects as variations in critical process parameters result in large variations in access latencies of hardware compo...
Madhu Mutyam, Narayanan Vijaykrishnan
ICC
2007
IEEE
170views Communications» more  ICC 2007»
14 years 4 months ago
Policy-Based QoS-Aware Packet Scheduling for CDMA 1x Ev-DO
— CDMA 1x Ev-DO is an evolution of the CDMA2000 3G wireless standard to enable high rate packet data services up to 2.4Mbps in Rev 0, 3.1Mbps in Rev A, and 4.9Mbps in Rev B. To s...
Jinho Hwang, M. Tamer Refaei, Hyeong-Ah Choi, Jae-...
INFOCOM
2007
IEEE
14 years 4 months ago
On the Detection of Signaling DoS Attacks on 3G Wireless Networks
— Third Generation (3G) wireless networks based on the CDMA2000 and UMTS standards are now increasingly being deployed throughout the world. Because of their complex signaling an...
Patrick P. C. Lee, Tian Bu, Thomas Y. C. Woo