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MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
14 years 3 months ago
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cor...
Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, P...
MICRO
2003
IEEE
152views Hardware» more  MICRO 2003»
14 years 3 months ago
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transient faults exist, but come at a cost. Designers...
Shubhendu S. Mukherjee, Christopher T. Weaver, Joe...
MICRO
2003
IEEE
100views Hardware» more  MICRO 2003»
14 years 3 months ago
The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System
Traditional software controlled data cache prefetching is often ineffective due to the lack of runtime cache miss and miss address information. To overcome this limitation, we imp...
Jiwei Lu, Howard Chen, Rao Fu, Wei-Chung Hsu, Bobb...
WWW
2003
ACM
14 years 10 months ago
Acting Accessibility: Scenario-based consideration of Web content accessibility for development and publishing communities
CT Conflict resolution of the ethical aspects of accessibility issues for Web communities can be facilitated by the judicious use of scenarios. Carefully designed scenarios permit ...
Liddy Nevile, Oliver K. Burmeister
ICRA
2003
IEEE
151views Robotics» more  ICRA 2003»
14 years 3 months ago
Microassembly of 3-D MEMS structures utilizing a MEMS microgripper with a robotic manipulator
This paper describes the process of bonding a MEMS (Micro-ElectroMechanical System) microgripper to the distal end of a robotic manipulator arm using a molten solder bonding techn...
Nikolai Dechev, William L. Cleghorn, James K. Mill...