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MICRO
2009
IEEE
14 years 4 months ago
2009
IEEE
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
MICRO
2009
IEEE
14 years 4 months ago
2009
IEEE
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
MICRO
2009
IEEE
14 years 4 months ago
2009
IEEE
With continued advances in CMOS technology, parameter variations are emerging as a major design challenge. Irregularities during the fabrication of a microprocessor and variations...
MICRO
2009
IEEE
14 years 4 months ago
2009
IEEE
Transactional Memory aims to provide a programming model that makes parallel programming easier. Hardware implementations of transactional memory (HTM) suffer from fewer overhead...
MICRO
2009
IEEE
14 years 4 months ago
2009
IEEE
With transistor miniaturization leading to an abundance of on-chip resources and uniprocessor designs providing diminishing returns, the industry has moved beyond single-core micr...