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MICRO
2010
IEEE
140views Hardware» more  MICRO 2010»
13 years 6 months ago
Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories
Emerging non-volatile memory technologies such as phase change memory (PCM) promise to increase storage system performance by a wide margin relative to both conventional disks and ...
Adrian M. Caulfield, Arup De, Joel Coburn, Todor I...
MICRO
2010
IEEE
172views Hardware» more  MICRO 2010»
13 years 6 months ago
Architectural Support for Fair Reader-Writer Locking
Abstract--Many shared-memory parallel systems use lockbased synchronization mechanisms to provide mutual exclusion or reader-writer access to memory locations. Software locks are i...
Enrique Vallejo, Ramón Beivide, Adriá...
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 6 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
MICRO
2010
IEEE
142views Hardware» more  MICRO 2010»
13 years 6 months ago
Virtual Snooping: Filtering Snoops in Virtualized Multi-cores
Virtualization has been rapidly expanding its applications in numerous server and desktop environments to improve the utilization and manageability of physical systems. Such prolif...
Daehoon Kim, Hwanju Kim, Jaehyuk Huh
MICRO
2010
IEEE
210views Hardware» more  MICRO 2010»
13 years 6 months ago
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
In a modern chip-multiprocessor system, memory is a shared resource among multiple concurrently executing threads. The memory scheduling algorithm should resolve memory contention...
Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor H...
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