New technologies such as 3D integration are becoming a new force that is keeping Moore’s law in effect in today’s nano era. By adding a third dimension in current 2D circuits...
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
The present paper is part of a larger effort to redesign, from the ground up, the best possible interconnect topologies for switchless multiprocessor computer systems. We focus he...
Different interconnection structures have been proposed to solve the performance limitation caused by scaling of on-chip global wires. In this paper, we give an overview of curre...
Yulei Zhang, Xiang Hu, Alina Deutsch, A. Ege Engin...