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113
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MICRO
2009
IEEE
15 years 10 months ago
2009
IEEE
With continued advances in CMOS technology, parameter variations are emerging as a major design challenge. Irregularities during the fabrication of a microprocessor and variations...
116
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MICRO
2009
IEEE
15 years 10 months ago
2009
IEEE
Transactional Memory aims to provide a programming model that makes parallel programming easier. Hardware implementations of transactional memory (HTM) suffer from fewer overhead...
125
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MICRO
2009
IEEE
15 years 10 months ago
2009
IEEE
Network-on-Chips (NoCs) are likely to become a critical shared resource in future many-core processors. The challenge is to develop policies and mechanisms that enable multiple ap...
143
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MICRO
2009
IEEE
15 years 10 months ago
2009
IEEE
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
128
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MICRO
2009
IEEE
15 years 10 months ago
2009
IEEE
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...