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PDP
1997
IEEE
14 years 28 days ago
The controlled logical clock--a global time for trace-based software monitoring of parallel applications in workstation clusters
Event tracing and monitoring of parallel applications are difficult if each processor has its own unsynchronized clock. A survey is given on several strategies to generate a glob...
Rolf Rabenseifner
INLG
2010
Springer
13 years 6 months ago
Finding Common Ground: Towards a Surface Realisation Shared Task
In many areas of NLP reuse of utility tools such as parsers and POS taggers is now common, but this is still rare in NLG. The subfield of surface realisation has perhaps come clos...
Anja Belz, Mike White, Josef van Genabith, Deirdre...
HPCN
1997
Springer
14 years 9 days ago
Boolean Function Manipulation on a Parallel System Using BDDs
This paper describes a distributed algorithm for Boolean function manipulation. The algorithm is based on Binary Decision Diagrams (BDDs), which are one of the most commonly used ...
F. Bianchi, Fulvio Corno, Maurizio Rebaudengo, Mat...
ISPD
1997
ACM
103views Hardware» more  ISPD 1997»
14 years 28 days ago
On two-step routing for FPGAS
We present results which show that a separate global and detailed routing strategy can be competitive with a combined routing process. Under restricted architectural assumptions, ...
Guy G. Lemieux, Stephen Dean Brown, Daniel Vranesi...
GLVLSI
1997
IEEE
105views VLSI» more  GLVLSI 1997»
14 years 29 days ago
OLIVIA: Objectoriented Logicsimulation Implementing the VITAL Standard
In a VHDL-based design flow for applicationspecific integrated circuits, VITAL provides a uniform methodology for developing ASIC libraries for signoff simulation. The VITAL Sta...
Josef Fleischmann, Rolf Schlagenhaft, Martin Pelle...