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SBCCI
2005
ACM
86views VLSI» more  SBCCI 2005»
14 years 1 months ago
Ultra-low power CMOS cells for temperature sensors
Temperature sensors and voltage references require cells that generate both PTAT (Proportional To Absolute Temperature) and NTC (Negative Temperature Coefficient) voltages. We pre...
Conrado Rossi, Pablo Aguirre
SBCCI
2005
ACM
122views VLSI» more  SBCCI 2005»
14 years 1 months ago
Phase noise performances of a cross-coupled CMOS VCO with resistor tail biasing
The Voltage Controlled Oscillator (VCO) is a fundamental block in RF IC architectures. Today’s wireless communication applications do require a high level of performances from s...
Sergio Gagliolo, Giacomo Pruzzo, Daniele D. Cavigl...
FCCM
2005
IEEE
151views VLSI» more  FCCM 2005»
14 years 1 months ago
Accelerating Applications by Mapping Critical Kernels on Coarse-Grain Reconfigurable Hardware in Hybrid Systems
In this paper, we propose a method for speeding-up applications by partitioning them between the reconfigurable hardware blocks of different granularity and mapping critical parts...
Michalis D. Galanis, Grigoris Dimitroulakos, Costa...
VLSI
2005
Springer
14 years 1 months ago
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
1 The increasing test data volume required to ensure high test quality when testing a System-on-Chip is becoming a problem since it (the test data volume) must fit the ATE (Automa...
Erik Larsson, Stina Edbom
VLSI
2005
Springer
14 years 1 months ago
Pareto Points in SRAM Design Using the Sleepy Stack Approach
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption a...
Jun-Cheol Park, Vincent John Mooney III