Sciweavers

240 search results - page 18 / 48
» vlsi 2005
Sort
View
VLSID
2005
IEEE
121views VLSI» more  VLSID 2005»
14 years 8 months ago
A Heuristic for Peak Power Constrained Design of Network-on-Chip (NoC) Based Multimode Systems
Designing NoC-based systems has become increasingly complex with support for multiple functionalities. Decisions regarding interconnections between the heterogeneous system compon...
Praveen Bhojwani, Rabi N. Mahapatra, Eun Jung Kim,...
DFT
2005
IEEE
103views VLSI» more  DFT 2005»
14 years 1 months ago
Methodologies and Algorithms for Testing Switch-Based NoC Interconnects
In this paper, we present two novel methodologies for testing the interconnect fabrics of network-on-chip (NoC) based chips. Both use the concept of recursive testing, with differ...
Cristian Grecu, Partha Pratim Pande, Baosheng Wang...
DFT
2005
IEEE
200views VLSI» more  DFT 2005»
14 years 1 months ago
Data Dependent Jitter (DDJ) Characterization Methodology
A new jitter model is developed using Matlab and Spice to analyze Data Dependent Jitter (DDJ) in serial data integrated circuits. The simulation results show that DDJ is dependent...
Kyung Ki Kim, Yong-Bin Kim, Fabrizio Lombardi
FCCM
2005
IEEE
96views VLSI» more  FCCM 2005»
14 years 1 months ago
Preliminary Report: FPGA Acceleration of Molecular Dynamics Computations
Abstract: Molecular Dynamics (MD) is of central importance to computational chemistry and its myriad applications. Here we show that, at even a preliminary stage of development, MD...
Yongfeng Gu, Tom Van Court, Douglas DiSabello, Mar...
FCCM
2005
IEEE
124views VLSI» more  FCCM 2005»
14 years 1 months ago
Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA
The CLA-EC is a model obtained by combining the concepts of cellular learning automata and evolutionary algorithms. The parallel structure of the CLA-EC makes it suitable for hard...
Arash Hariri, Reza Rastegar, Morteza Saheb Zamani,...