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GLVLSI
2005
IEEE
67views VLSI» more  GLVLSI 2005»
14 years 1 months ago
Energy recovery clocked dynamic logic
Energy recovery clocking results in significant energy savings in clock distribution networks as compared to conventional squarewave clocking. However, since energy recovery clock...
Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen,...
GLVLSI
2005
IEEE
85views VLSI» more  GLVLSI 2005»
14 years 1 months ago
Utilizing don't care states in SAT-based bounded sequential problems
Boolean Satisfiability (SAT) solvers are popular engines used throughout the verification world. Bounded sequential problems such as bounded model checking and bounded sequentia...
Sean Safarpour, Görschwin Fey, Andreas G. Ven...
GLVLSI
2005
IEEE
147views VLSI» more  GLVLSI 2005»
14 years 1 months ago
1-V 7-mW dual-band fast-locked frequency synthesizer
This paper presents a fully integrated 1-V, dual band, fastlocked frequency synthesizer for IEEE 802.11 a/b/g WLAN applications. It can synthesize frequencies in the range of 2.4 ...
Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen
VLSID
2005
IEEE
105views VLSI» more  VLSID 2005»
14 years 1 months ago
Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines
The primary advantage of using 3D-FPGA over 2D-FPGA is that the vertical stacking of active layers reduce the Manhattan distance between the components in 3D-FPGA than when placed...
R. Manimegalai, E. Siva Soumya, V. Muralidharan, B...
GLVLSI
2005
IEEE
120views VLSI» more  GLVLSI 2005»
14 years 1 months ago
3D module placement for congestion and power noise reduction
3D packaging via System-On-Package (SOP) is a viable alternative to System-On-Chip (SOC) to meet the rigorous requirements of today’s mixed signal system integration. In this wo...
Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh