240 search results - page 45 / 48 » vlsi 2005 |
VLSID
2005
IEEE
2005
IEEE
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model
14 years 1 months ago
One of the emerging challenges in formal property verification (FPV) technology is the problem of deciding whether sufficient properties have been written to cover the design in...
VLSID
2005
IEEE
14 years 1 months ago
2005
IEEE
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...
ASPDAC
2005
ACM
14 years 1 months ago
2005
ACM
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
SBCCI
2005
ACM
14 years 1 months ago
2005
ACM
Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer manageme...
SBCCI
2005
ACM
14 years 1 months ago
2005
ACM
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...