We describe a technique to generate critical hazard-free tests for self-timed control circuits build using a macromodule library, in a partial scan based DFT environment. Wepropos...
A new approach for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking ex...
Accumulators based on addition or subtraction can be used as test pattern generators. Some circuits, however, require long test lengths if the parameters of the accumulator are no...