ATPG for scan chain latches and flip-flops

A new approach for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking experiment to each bistable element in the circuit while checking their response. Such tests guarantee the detection of all detectable combinational defects inside the bistable elements. The algorithm is implemented by modifying an existing stuck-at combinational test pattern generator. The number of test patterns generated by the new program is comparable to the number of traditional stuck-at patterns. This shows that this approach is practical for large circuits.

• Type: Conference
• Year: 1997
• Where: VTS
• Authors: Samy Makar, Edward J. McCluskey
• Keywords: Bistable Elements, Detectable Combinational Defects, Hardware, Test Patterns, VTS 1997