We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
Run-length codes and their variants have recently been shown to be very effective for compressing system-on-achip (SOC) test data. In this paper, we analyze the Golomb code, the c...
Anshuman Chandra, Krishnendu Chakrabarty, Rafael A...
The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is ther...
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan M...
The performance of face verification systems has steadily improved over the last few years, mainly focusing on models rather than on feature processing. State-of-the-art methods o...
Statistical models of shape and appearance have been successfully used in face modeling, tracking and synthesis. In this paper we describe experiments using appearance models for ...