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DFT
2007
IEEE
103views VLSI» more  DFT 2007»
14 years 2 months ago
Lazy Error Detection for Microprocessor Functional Units
We propose and evaluate the use of lazy error detection for a superscalar, out-of-order microprocessor’s functional units. The key insight is that error detection is off the cri...
Mahmut Yilmaz, Albert Meixner, Sule Ozev, Daniel J...
EUC
2006
Springer
13 years 11 months ago
Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit
Extracting appropriate custom instructions is an important phase for implementing an application on an extensible processor with a reconfigurable functional unit (RFU). Custom inst...
Farhad Mehdipour, Hamid Noori, Morteza Saheb Zaman...
CASES
2001
ACM
13 years 11 months ago
Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures
In this paper we describe a design exploration methodology for clustered VLIW architectures. The central idea of this work is a set of three techniques aimed at reducing the cost ...
Marcio Buss, Rodolfo Azevedo, Paulo Centoducatte, ...
MICRO
1994
IEEE
85views Hardware» more  MICRO 1994»
13 years 11 months ago
A high-performance microarchitecture with hardware-programmable functional units
This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Throu...
Rahul Razdan, Michael D. Smith
VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
14 years 8 months ago
Temperature and Process Variations Aware Power Gating of Functional Units
Technology scaling has resulted in an exponential increase in the leakage power as well as the variations in leakage power of fabricated chips. Functional units (FUs), like Intege...
Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sar...