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    EURODAC
    1995
    IEEE
    101views VHDL» more  EURODAC 1995»
    Exploiting power-up delay for sequential optimization
    14 years 7 months ago
    Exploiting power-up delay for sequential optimization
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    Recent work has identified the notion of safe replacement for sequential synchronousdesigns that may not have reset hardware or even explicitly known initial states. Safe replace...
    Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K....
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