Exploiting power-up delay for sequential optimization

Recent work has identified the notion of safe replacement for sequential synchronousdesigns that may not have reset hardware or even explicitly known initial states. Safe replacementrequiresthat a replacement design be indistinguishable from the original from the very first clock cycle after power-up. However, in almost any realistic application, the design is allowed to stabilize for many clock cycles before it is used. In this paper, we investigate the safety of a replacement if the replacement design is allowed to be clocked some cycles (that is, delayed) with arbitrary inputs before the design is reset. Having argued the safety of “delay” replacements, we investigate a new method of sequential optimization based upon the notion. We present experimental results to demonstrate that significant area optimizations can be gained by using this new notion of delay replaceability, and that there is a trade-off between the allowed number of clock cycles after power-up and the amount...

• Type: Conference
• Year: 1995
• Where: EURODAC
• Authors: Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton
• Keywords: Clock Cycles, EURODAC 1995, Replacement Design, VHDL, first Clock Cycle