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31
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ISLPED
1999
ACM
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ISLPED 1999
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Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
14 years 3 months ago
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iacoma.cs.uiuc.edu
Modern microprocessors employ one or two levels of on-chip cachesto bridge the burgeoning speeddisparities between the processor and the RAM. These SRAM caches are a major source ...
Kanad Ghose, Milind B. Kamble
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