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35
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DATE
2008
IEEE
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DATE 2008
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Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation
14 years 6 months ago
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www.engr.uconn.edu
— Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shi...
Jeremy Lee, Sumit Narayan, Mike Kapralos, Mohammad...
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