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ISLPED
2005
ACM
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ISLPED 2005
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Complexity reduction in an nRERL microprocessor
14 years 6 months ago
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www.cecs.uci.edu
We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers...
Seokkee Kim, Soo-Ik Chae
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