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IPPS
2000
IEEE
14 years 6 days ago
Complexity Bounds for Lookup Table Implementation of Factored Forms in FPGA Technology Mapping
We consider technology mapping from factored form binary leaf-DAG to lookup tables LUTs, such as those found in eld programmable gate arrays. Polynomial time algorithms exist f...
Wenyi Feng, Fred J. Meyer, Fabrizio Lombardi
IPPS
2000
IEEE
14 years 6 days ago
Present and Future Needs of Free-Space Optical Interconnects
Over the last decade significant progress in optoelectronic devices and their integration techniques have made Free-Space Optical Interconnects (FSOI) one of the few physical appro...
Sadik C. Esener, Philippe J. Marchand
IPPS
2000
IEEE
14 years 6 days ago
Speed vs. Accuracy in Simulation for I/O-Intensive Applications
This paper presents a family of simulators that have been developed for data-intensive applications, and a methodology to select the most efficient one based on a usersupplied req...
Hyeonsang Eom, Jeffrey K. Hollingsworth
IPPS
2000
IEEE
14 years 6 days ago
Parallel Maximum-Likelihood Inversion for Estimating Wavenumber-Ordered Spectra in Emission Spectroscopy
We introduce a parallelization of the maximumlikelihood cosine transform. This transform consists of a computationally intensive iterative fitting process, but is readily decompo...
Hoda El-Sayed, Marc Salit, John Travis, Judith Ell...
IPPS
2000
IEEE
14 years 6 days ago
A Distributed Computing Demonstration System Using FSOI Inter-processor Communication
Presented here is a computational system which uses free−space optical interconnect (FSOI) communication between processing elements to perform distributed calculations. Technolo...
Jeremy Ekman, Christoph Berger, Fouad E. Kiamilev,...
IPPS
2000
IEEE
14 years 6 days ago
Implementation of Finite Lattices in VLSI for Fault-State Encoding in High-Speed Networks
In this paper the propagation of information about fault states and its implementation in high-speed networks is discussed. The algebraic concept of a lattice partial ordered set ...
Andreas C. Döring, Gunther Lustig
IPPS
2000
IEEE
14 years 6 days ago
The Memory Bandwidth Bottleneck and its Amelioration by a Compiler
As the speed gap between CPU and memory widens, memory hierarchy has become the primary factor limiting program performance. Until now, the principal focus of hardware and softwar...
Chen Ding, Ken Kennedy