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CCR
2010
80views more  CCR 2010»
13 years 9 months ago
YAMR: yet another multipath routing protocol
Igor Ganichev, Bin Dai, Brighten Godfrey, Scott Sh...
CCR
2010
151views more  CCR 2010»
13 years 9 months ago
iNFAnt: NFA pattern matching on GPGPU devices
This paper presents iNFAnt, a parallel engine for regular expression pattern matching. In contrast with traditional approaches, iNFAnt adopts non-deterministic automata, allowing ...
Niccolo Cascarano, Pierluigi Rolando, Fulvio Risso...
CCGRID
2010
IEEE
13 years 9 months ago
Low-Cost Tuning of Two-Step Algorithms for Scheduling Mixed-Parallel Applications onto Homogeneous Clusters
Due to the strong increase of processing units available to the end user, expressing parallelism of an algorithm is a major challenge for many researchers. Parallel applications ar...
Sascha Hunold
CCGRID
2010
IEEE
13 years 9 months ago
Dynamic Load-Balanced Multicast for Data-Intensive Applications on Clouds
Data-intensive parallel applications on clouds need to deploy large data sets from the cloud's storage facility to all compute nodes as fast as possible. Many multicast algori...
Tatsuhiro Chiba, Mathijs den Burger, Thilo Kielman...
CCGRID
2010
IEEE
13 years 9 months ago
File-Access Characteristics of Data-Intensive Workflow Applications
This paper studies five real-world data intensive workflow applications in the fields of natural language processing, astronomy image analysis, and web data analysis. Data intensiv...
Takeshi Shibata, SungJun Choi, Kenjiro Taura
IEEEPACT
2009
IEEE
13 years 9 months ago
ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs
Abstract--Chip-MultiProcessor (CMP) architectures are becoming more and more popular as an alternative to the traditional processors that only extract instruction-level parallelism...
Carlos Luque, Miquel Moretó, Francisco J. C...
IEEEPACT
2009
IEEE
13 years 9 months ago
FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery
Abstract--Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored. Current...
Marc Lupon, Grigorios Magklis, Antonio Gonzá...
IEEEPACT
2009
IEEE
13 years 9 months ago
Adaptive Locks: Combining Transactions and Locks for Efficient Concurrency
Transactional memory is being advanced as an alternative to traditional lock-based synchronization for concurrent programming. Transactional memory simplifies the programming mode...
Takayuki Usui, Reimer Behrends, Jacob Evans, Yanni...
IEEEPACT
2009
IEEE
13 years 9 months ago
Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor
Efficiently using the hardware capabilities of the Cell processor, a heterogeneous chip multiprocessor that uses several levels of parallelism to deliver high performance, and bei...
Tarik Saidani, Joel Falcou, Claude Tadonki, Lionel...