DATE
2009
IEEE
14 years 6 months ago
2009
IEEE
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
CSE
2009
IEEE
14 years 6 months ago
2009
IEEE
—Ceremonies are a useful tool to establish trust in scenarios where protocols operate. They describe a greater range of issues not taken into account by protocol designers. We ta...
SAS
2009
Springer
14 years 6 months ago
2009
Springer
There are many programming situations where it would be convenient to conceal the meaning of code, or the meaning of certain variables. This can be achieved through program transfo...
CAV
2009
Springer
14 years 6 months ago
2009
Springer
CAV
2009
Springer
14 years 6 months ago
2009
Springer
Systems and Networks on Chips (NoCs) are a prime design focus of many hardware manufacturers. In addition to functional verification, which is a difficult necessity, the chip desi...
CAV
2009
Springer
14 years 6 months ago
2009
Springer
In this paper we consider two-player zero-sum payoff games on finite graphs, both in the deterministic as well as in the stochastic setting. In the deterministic setting, we consi...
CAV
2009
Springer
14 years 6 months ago
2009
Springer
CAV
2009
Springer
14 years 6 months ago
2009
Springer
The DPLL approach to the Boolean satisfiability problem (SAT) is a combination of search for a satisfying assignment and logical deduction, in which each process guides the other....
VMCAI
2010
Springer
14 years 6 months ago
2010
Springer
VMCAI
2010
Springer
14 years 6 months ago
2010
Springer
This paper upgrades Regular Linear Temporal Logic (RLTL) with past operators and complementation. RLTL is a temporal logic that extends the expressive power of linear temporal logi...