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MICRO
2002
IEEE
121views Hardware» more  MICRO 2002»
13 years 11 months ago
Convergent scheduling
Convergent scheduling is a general framework for instruction scheduling and cluster assignment for parallel, clustered architectures. A convergent scheduler is composed of many ind...
Walter Lee, Diego Puppin, Shane Swenson, Saman P. ...
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 11 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 11 months ago
Generating physical addresses directly for saving instruction TLB energy
Power consumption and power density for the Translation Lookaside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as w...
Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. K...
MICRO
2002
IEEE
119views Hardware» more  MICRO 2002»
13 years 11 months ago
Microarchitectural support for precomputation microthreads
Research has shown that precomputation microthreads can be useful for improving branch prediction and prefetching. However, it is not obvious how to provide the necessary microarc...
Robert S. Chappell, Francis Tseng, Adi Yoaz, Yale ...
ISCA
2002
IEEE
141views Hardware» more  ISCA 2002»
13 years 11 months ago
SADL: Simulation Architecture Description Language
This paper introduces the Simulation Architecture Description Language (SADL) developed at the National Aeronautics and Space Administration's Marshall Space Flight Center to...
Kenneth G. Ricks, John M. Weirs, B. Earl Wells
ISCA
2002
IEEE
174views Hardware» more  ISCA 2002»
13 years 11 months ago
Efficient Task Partitioning Algorithms for Distributed Shared Memory Systems
In this paper, we consider the tree task graphs which arise from many important programming paradigms such as divide and conquer, branch and bound etc., and the linear task-graphs...
Sibabrata Ray, Hong Jiang
ISCA
2002
IEEE
104views Hardware» more  ISCA 2002»
13 years 11 months ago
Speculative Dynamic Vectorization
Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also pre...
Alex Pajuelo, Antonio González, Mateo Valer...
ISCA
2002
IEEE
82views Hardware» more  ISCA 2002»
13 years 11 months ago
Queue Pair IP: A Hybrid Architecture for System Area Networks
Philip Buonadonna, David E. Culler
COMPUTER
1998
119views more  COMPUTER 1998»
13 years 11 months ago
Virtual Memory: Issues of Implementation
ion layer3,4 hides hardware particulars from the higher levels of software but can also compromise performance and compatibility; the higher levels of software often make unwitting...
Bruce L. Jacob, Trevor N. Mudge
SIGMETRICS
2000
ACM
147views Hardware» more  SIGMETRICS 2000»
13 years 11 months ago
High-capacity Internet middleware: Internet caching system architectural overview
Previous studies measuring the performance of general-purpose operating systems running large-scale Internet server applications, such as proxy caches, have identified design defi...
Gary Tomlinson, Drew Major, Ron Lee