Due to the exponential growth of both design complexity and the number of gates per pin, functional debugging has emerged as a critical step in the development of a system-on-chip...
The intellectual property (IP) business model is vulnerable to a number of potentially devastating obstructions, such as misappropriation and intellectual property fraud. We propo...
We survey the state-of-the-art in real-time operating systems (RTOSs) from the system synthesis point of view. RTOSs have a very long research history which provides important the...
Serge Hustin, Miodrag Potkonjak, Eric Verhulst, Wa...
In this paper, we propose a high-level variable selection for partial-scan approach to improve the testability of digital systems. The testability of a design is evaluated at the ...
We present a fast, dynamic fault coverage estimation technique for sequential circuits that achieves high degrees of accuracy by signi cantly reducing the number of injected fault...
This paper presents a novel concurrent fault simulator (called CONCERT) for nonlinear analog circuits. Three primary techniques in CONCERT, including fault ordering, state predict...
We consider the problem of scheduling the mixed workload of both sporadic (on-line) and periodic (off-line) tasks on variable voltage processor to optimize power consumption while...
We present a method for optimizing and automating component and transistor sizing for CMOS operational amplifiers. We observe that a wide variety of performance measures can be fo...
Maria del Mar Hershenson, Stephen P. Boyd, Thomas ...
Presented in this paper are 1) information-theoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy...