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36
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DATE
2010
IEEE
163
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DATE 2010
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Optimizing equivalence checking for behavioral synthesis
14 years 5 months ago
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web.cecs.pdx.edu
Abstract—Behavioral synthesis is the compilation of an Electronic system-level (ESL) design into an RTL implementation. We present a suite of optimizations for equivalence checki...
Kecheng Hao, Fei Xie, Sandip Ray, Jin Yang
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