Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entir...
This paper is concerned with application of standard wireless COTS protocols to space. Suitability of commercially available wireless sensor mote kits for communication inside and...
Tanya Vladimirova, Christopher P. Bridges, George ...
Abstract— A programmable analog array inspired from neuronal spike event coding is presented. A configurable event block forms the basic building block of the programmable array...
Thomas Jacob Koickal, Alister Hamilton, Luiz C. P....
This paper introduces Perplexus, a European project that aims to develop a scalable hardware platform made of custom reconfigurable devices endowed with bio-inspired capabilities...
This work describes an algebraic based design strategy targeting area optimization in reconfigurable computer technology (FPGA). Area optimization is a major issue as smaller comp...
Gabriel Marchesan Almeida, Eduardo Augusto Bezerra...
Fault Tolerance is an increasing challenge for integrated circuits due to semiconductor technology scaling. This paper looks at how artificial evolution may be tuned to the creat...
In this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. The inputs of...
Caaliph Andriamisaina, Emmanuel Casseau, Philippe ...
This paper presents a mechanism for the separation of control and data flow in NoC-based SoCs consisting of multiple heterogeneous reconfigurable IP cores. This mechanism enables ...
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...
System-on-Chip devices containing both conventional and reconfigurable circuits are increasing in popularity. However the on-chip debug support infrastructure required to aid syst...