Fault Tolerance is an increasing challenge for integrated circuits due to semiconductor technology scaling. This paper looks at how artificial evolution may be tuned to the creation of novel redundancy structures which may be applied to meet this challenge. However, as these structures are unknown it is a challenge in itself to tune evolution to create them. As such, no solution has yet been found. This paper provides a discussion about the issues addressed and experiments conducted and thus provides an overview of the lessons learned in this work.
Asbjørn Djupdal, Pauline C. Haddow