Sciweavers

ASPDAC
2004
ACM
113views Hardware» more  ASPDAC 2004»
14 years 4 months ago
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction
- Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a poly...
Chi-Chou Kao, Yen-Tai Lai
ASPDAC
2004
ACM
74views Hardware» more  ASPDAC 2004»
14 years 4 months ago
Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming
- In this paper, a novel strategy for designing the heterogeneous-tree multiplexer is proposed. We build the multiplexer delay model by curve fitting and then formulate the heterog...
Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou
ASPDAC
2004
ACM
94views Hardware» more  ASPDAC 2004»
14 years 4 months ago
Improving simulation-based verification by means of formal methods
The design of complex systems is largely ruled by the time needed for verification. Even though formal methods can provide higher reliability, in practice often simulation based ve...
Görschwin Fey, Rolf Drechsler
ASPDAC
2004
ACM
103views Hardware» more  ASPDAC 2004»
14 years 4 months ago
Design and implementation of a secret key steganographic micro-architecture employing FPGA
In the well-known "prisoners' problem", a representative example of steganography, two persons attempt to communicate covertly without alerting the warden. One appr...
Hala A. Farouk, Magdy Saeb
ASPDAC
2004
ACM
144views Hardware» more  ASPDAC 2004»
14 years 4 months ago
Verification of timed circuits with symbolic delays
When time is incorporated in the specification of discrete systems, the complexity of verification grows exponentially. When the temporal behavior is specified with symbols, the ve...
Robert Clarisó, Jordi Cortadella
ASPDAC
2004
ACM
79views Hardware» more  ASPDAC 2004»
14 years 4 months ago
NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO
Abstract--A parasitic-aware RF synthesis tool based on a nondominated sorting genetic algorithm (NSGA) is introduced. The NSGA-based optimizer casts the design problem as a multi-o...
Min Chu, David J. Allstot, Jeffrey M. Huard, Kim Y...
ASPDAC
2004
ACM
79views Hardware» more  ASPDAC 2004»
14 years 4 months ago
Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocesso
Abstract - We propose an integrated archltectural/physicdplanning approach named priority assignment optimization to mioimize the current surge in high performance power eifkient c...
Yiran Chen, Kaushik Roy, Cheng-Kok Koh
ASPDAC
2004
ACM
120views Hardware» more  ASPDAC 2004»
14 years 5 months ago
Efficient octilinear Steiner tree construction based on spanning graphs
--Octilinear interconnect is a promising technique to shorten wire lengths. We present two practical heuristic octilinear Steiner tree (OSMT) algorithms in the paper. They are both...
Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Y...
ASPDAC
2004
ACM
120views Hardware» more  ASPDAC 2004»
14 years 5 months ago
Temporal floorplanning using 3D-subTCG
Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this paper, we use a novel topo...
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-...