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    IEEE
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    Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis
    14 years 5 months ago
    Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis
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    Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. Howev...
    Tiberiu Chelcea, Girish Venkataramani, Seth Copen ...
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