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ATS
2004
IEEE
109views Hardware» more  ATS 2004»
14 years 3 months ago
Reconfiguration for Enhanced ALternate Test (REALTest) of Analog Circuits
An efficient design for test methodology to increase the test yield of analog circuits is presented. It is assumed that the analog circuits are tested using alternate tests that r...
Ganesh Srinivasan, Shalabh Goyal, Abhijit Chatterj...
ATS
2004
IEEE
126views Hardware» more  ATS 2004»
14 years 3 months ago
Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumptio
Test data volume and scan power are two major concerns in SoC test. In this paper we present an alternative run-length coding method through scan chain reconfiguration to reduce b...
Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Ya...
ATS
2004
IEEE
97views Hardware» more  ATS 2004»
14 years 3 months ago
Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores
TIS (Test Instruction Set) is an instruction level technique for CPU core self-testing. This method is based on enhancing a CPU instruction set with test instructions. TIS replace...
Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin N...
ATS
2004
IEEE
87views Hardware» more  ATS 2004»
14 years 3 months ago
Low Power BIST with Smoother and Scan-Chain Reorder
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...
Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu
ATS
2004
IEEE
69views Hardware» more  ATS 2004»
14 years 3 months ago
Pair Balance-Based Test Scheduling for SOCs
Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li
ATS
2004
IEEE
93views Hardware» more  ATS 2004»
14 years 3 months ago
Hybrid BIST Test Scheduling Based on Defect Probabilities
1 This paper describes a heuristic for system-on-chip test scheduling in an abort-on-fail context, where the test is terminated as soon as a defect is detected. We consider an hybr...
Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
ATS
2004
IEEE
116views Hardware» more  ATS 2004»
14 years 3 months ago
Testing for Missing-Gate Faults in Reversible Circuits
Logical reversibility occurs in low-power applications and is an essential feature of quantum circuits. Of special interest are reversible circuits constructed from a class of rev...
John P. Hayes, Ilia Polian, Bernd Becker
ATS
2004
IEEE
108views Hardware» more  ATS 2004»
14 years 3 months ago
Rapid and Energy-Efficient Testing for Embedded Cores
Conventional serial connection of internal scan chains brings the power and time penalty. A novel parallel core wrapper design (pCWD) approach is presented in this paper for reduc...
Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman ...