Rapid and Energy-Efficient Testing for Embedded Cores

Conventional serial connection of internal scan chains brings the power and time penalty. A novel parallel core wrapper design (pCWD) approach is presented in this paper for reducing test power and test application time. The pCWD utilizes overlapping scan slices to reduce the number of scan slices loading. Experimental results on d695 of ITC2002 benchmark demonstrated that, about 2X shift time and 20X test power reduction can be achieved.

• Type: Conference
• Year: 2004
• Where: ATS
• Authors: Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra
• Keywords: ATS 2004, Hardware, Internal Scan Chains, Scan Slices, Test Power