Sciweavers

BIBE
2007
IEEE
126views Bioinformatics» more  BIBE 2007»
14 years 1 months ago
FPGA Acceleration of Phylogeny Reconstruction for Whole Genome Data
In this paper we describe our design and characterization of a co-processor architecture to accelerate median-based phylogenetic reconstruction for generearrangement data. Our curr...
Jason D. Bakos, Panormitis E. Elenis, Jijun Tang
SBACPAD
2007
IEEE
129views Hardware» more  SBACPAD 2007»
14 years 5 months ago
Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications
The necessity of devising novel thread-level speculation (TLS) techniques has become extremely important with the growing acceptance of multi-core architectures by the industry. H...
Md. Mafijul Islam
ICCD
2002
IEEE
88views Hardware» more  ICCD 2002»
14 years 8 months ago
Improving Processor Performance by Simplifying and Bypassing Trivial Computations
During the course of a program’s execution, a processor performs many trivial computations; that is, computations that can be simplified or where the result is zero, one, or equ...
Joshua J. Yi, David J. Lilja