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CDES
2006

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A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs

14 years 7 days ago

In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...

Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia

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